The trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes and increase the number of devices fabricated on the integrated circuit has required smaller isolation areas between devices. The active areas in which devices are built are isolated by a layer of oxide known as field oxide. However, the technology used to isolate active areas has not kept pace with the everdecreasing device geometries.
Isolation techniques should meet a variety of requirements. First, active areas should be in close proximity. Second, the lateral encroachment or tapering of the field oxide into the active areas, known as "birdbeaking", should be minimized. Third, the leakage current between active devices should be negligible. Fourth, the process for forming the field oxide regions must be easily adapted for use with standard integrated circuit fabrication process flows and not adversely affect device parameters.
Many methods have been proposed over the years to reduce the bird's beak of a field oxide region when isolating devices. One such method of isolating devices, LOCOS, local oxidation of silicon, produces regions of insulating silicon dioxide between devices. The LOCOS process was a great technological improvement in reducing the area needed for the isolation regions and decreasing some parasitic capacitances.
In LOCOS, silicon nitride is deposited and patterned over a stress relief pad oxide layer. The silicon nitride layer is retained over the area over where further oxidation is not desired. Thus, the silicon nitride is etched to expose a portion of the pad oxide where the field oxide is to be grown. After the thermal oxidation of the exposed pad oxide to form the field oxide regions, the silicon nitride layer is removed.
Several problems occurred, however, with LOCOS. Thermal oxidation in the original LOCOS form always incurred lateral encroachment, or birdbeaking, of the field oxide into the active areas growing under the silicon nitride mask. This birdbeaking is a substantial sacrifice of active areas that becomes significant for feature sizes less than 1.5 microns. The active area becomes smaller than the initial dimensions of the nitride layer.
Attempts to suppress birdbeaking in LOCOS, such as forming thicker nitride layers, caused stress-related defects in the nearby substrate due to the difference in the thermal coefficients of expansion between the silicon substrate and the silicon nitride layers. Process complexity also increased substantially in attempting to avoid these stress-related defects. To achieve submicron geometries, there can be little or no physical loss of the active areas as occurs with the birdbeaking phenomenon.
To reduce the bird's beak effect, there has been proposed the use of a polysilicon layer between the nitride layer and the pad oxide layer as more fully described in U.S. Pat. No. 4,407,696, issued Oct. 4, 1983 to Han et al. The use of the polysilicon layer in the LOCOS process, known as poly-buffered LOCOS or PBLOCOS, is used to reduce oxidation induced stacking faults resulting from the stress caused by the different thermal coefficients of expansion between the silicon substrate and a thick silicon nitride layer overlying the substrate. As described more fully in the publication "Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", J. Electrochem. Soc., Vol 138, No. Jul. 7, 1991 by Tin-hwang Lin et al, the polysilicon layer absorbs the excessive stress caused by the silicon nitride and prevents the lateral encroachment of oxidants, thus reducing the bird's beak.
The field oxide layer grown using poly-buffered LOCOS thus comprises the oxide derived from the silicon substrate, a portion of the pad oxide layer and oxide derived from the polysilicon layer. Afterwards, the nitride layer, the polysilicon layer and the pad oxide are etched. The poly-buffered LOCOS process reduces the bird's beak area over standard LOCOS resulting in less encroachment of the tapered portion of the field oxide into the active areas under the nitride mask. However, the bird's beak effect still remains, due to the oxidation of the polysilicon layer. In addition, the complexity of the process increases substantially in order to achieve the resulting structure.
In order to further decrease the bird's beak area using poly-buffered LOCOS, it has been proposed to surround the polysilicon layer with silicon nitride, as more fully described in U.S. Pat. No. 4,260,229, issued Nov. 9, 1993 to Hodges et al. and incorporated herein. As with standard poly-buffered LOCOS, the stress caused between the thick nitride layer over a thin pad oxide and the silicon substrate is reduced by the addition of the polysilicon layer. The bird's beak is further reduced due to the encapsulation of the polysilicon in silicon nitride. The oxidation of the polysilicon is reduced or eliminated. None of the polysilicon layer thus forms any part of the thermally grown field oxide. The resulting bird's beak is thus substantially reduced. Also in an effort to decrease the bird's beak, it has also been proposed to use a nitrogen implant into the polysilicon layer followed by an annealing step to encapsulate the polysilicon layer in silicon nitride, as more fully described in U.S. Pat. No. 5,192,707, issued on Mar. 9, 1993 to Hodges, et al. None of the polysilicon layer should thus form any part of the thermally grown field oxide. The resulting bird's beak area under the nitride mask is thus substantially reduced.
Each of these ideas help to reduce the bird's beak at the edge of field oxides but thick field oxides add to the topography of the surface of the wafer. Global planar isolation surfaces are desirable for submicron design rule technologies, particularly under 0.5 microns. Transistor gate patterns are subject to reflective notching problems from the topographies created by thick field oxide isolation regions. Anti-Reflective coatings and increased die loading in photoresists are designed to decrease the reflective notching problems, but inherently add to process complexity and cost, decreased pattern quality and increased exposure times. Some planarizing isolation processes are often times very expensive, such as Chemical Mechanical Polishing (CMP). Other planarizing techniques create high defectivities such as the well-known techniques: buried-oxide isolation technology (BOX) and recessed sealed-interface local oxidation technology (SILO and POP-SILO). Yet other techniques are very complex such as the nitride encapsulated polybuffered LOCOS process (NEPBL). Finally, other techniques simply do not work as well such as trench isolation, and spin-on-glass fills with etchback processes. It would be desirable to have a process of forming a field oxide region with a reduced bird's beak which also forms a substantially planar surface.
It is therefore an object of the present invention to provide a method of forming an isolation region with a reduced bird's beak.
It is a further object of the present invention to provide such a method which provides more planarization for subsequent processing steps which will improve step coverage of subsequently formed layers.
It is yet a further object of the present invention which utilizes standard integrated circuit processing steps.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.